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D a t a Sh e e t , V 2. 0 , D e c e m b e r 2 0 0 3
H Y E 1 8 P 1 6 1 6 1 A C - 7 0 /L 7 0 H Y E 1 8 P 1 6 1 6 1 A C - 8 5 /L 8 5
1 6 M As yn c h r o n o u s/ P a g e C e ll ul a r R A M C e ll u la r R AM
M e m o r y P r o d u c ts
Never
stop
thinking.
Edition 2003-12-16 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Da t a S h e e t , V2 . 0 , D ec e m b e r 2 0 0 3
H Y E 1 8 P 1 6 1 6 1 A C - 7 0 /L 7 0 H Y E 1 8 P 1 6 1 6 1 A C - 8 5 /L 8 5
1 6 M As yn c h r o n o u s/ P a g e C e ll ul a r R A M C e ll u la r R AM
M e m o r y P r o d u c ts
Never
stop
thinking.
HYE18P16161AC-70/L70, HYE18P16161AC-85/L85 Revision History: Previous Version: Page all all 2003-12-16 1.9 (Target data sheet) V2.0
Subjects (major changes since last revision) 2nd bin of Icc2 added. Marking for low-power part puts "L" in the place of "-" tLZ, tBLZ, tOLZ are adjusted
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Template: mp_a4_v2.0_2003-06-06.fm
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.1 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.4 2.4.1 2.5 2.6 2.7 3 3.1 3.2 3.3 3.4 4 5 5.1 6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 HYE18P16161AC(-/L)70/85 Ball Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 HYE18P16161AC(-/L)70/85 Ball Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Access To The Control Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refresh Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Partial Array Self Refresh (PASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deep Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Compensated Self Refresh (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Saving Potential in Standby When Applying PASR, TCSR or DPD . . . . . . . . . . . . . . . . . . . Page Mode Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deep Power Down Mode Entry/ Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Power & DC Operation Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 15 16 17 18 18 18 19 20 21 23 26 26 27 27 27 28 28
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Appendix A: Low-Frequency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Asynchronous Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Appendix B: S/W Register Entry Mode ("4-cycle method") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Data Sheet
5
V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21
CellularRAM - Interface Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Standard Ballout - HYE18P16161AC(-/L)70/85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Refresh Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Control Register Write Access Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PASR Programming Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PASR Configuration Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Asynchronous Read - Address Controlled (CS1 = OE = VIL, WE = VIH, UB and/or LB = VIL, ZZ = VIH) 20 Asynchronous Read (WE = VIH, ZZ = VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Asynchronous Page Read Mode (ZZ = VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Asynchronous Write - WE Controlled (OE = VIH or VIL, ZZ = VIH). . . . . . . . . . . . . . . . . . . . . . . . . . 23 Asynchronous Write - CS1 Controlled (OE = VIH or VIL, ZZ = VIH) . . . . . . . . . . . . . . . . . . . . . . . . . 23 Asynchronous Write - UB, LB Controlled (OE = VIH or VIL, ZZ = VIH) . . . . . . . . . . . . . . . . . . . . . . . 24 Asynchronous Write to Control Register (OE = VIH or VIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Deep Power Down Entry/ Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 P-VFBGA-48 (Plastic Very Thin Fine Pitch Ball Grid Array Package) . . . . . . . . . . . . . . . . . . . . . . 29 Low Frequency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 S/W Register Entry timing (Address input = FFFFFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 RCR Mapping in S/W Register Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Data Sheet
6
V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 13 Table 12
Product Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ball Description - HYE18P16161AC(-/L)70/85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby Currents When Applying PASR, TCSR or DPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Parameters - Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Parameters - Asynchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPD/ ZZ Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.8 11 13 13 18 22 25 26 27 27 27 28 28
Data Sheet
7
V2.0, 2003-12-16
16M Asynchronous/Page CellularRAM CellularRAM
HYE18P16161AC-70/L70 HYE18P16161AC-85/L85
1
1.1
* * * * * * * *
Overview
Features
High density (1T1C-cell) Synchronous 16-Mbit Pseudo-Static RAM Designed for cell phone applications (CellularRAM) Functional-compatible to conventional low power asynchronous SRAM devices Organization 1M x 16 Refresh-free operation 1.8 V single power supply (VDD and VDDQ) Support of 2.5V and 3.0V I/O voltage options (VDDQ) Low power optimized design - ISTANDBY = 70 A for L-part and 100 A for standard part (16M), data retention mode - IDPD = < 25 A (16M), non-data retention mode
*
Low power features (partly adopted from the JEDEC standardized low power SDRAM specifications) - Temperature Compensated Self-Refresh (TCSR) - Partial Array Self-Refresh (PASR) - Deep Power Down Mode (DPD)
* * * *
70 ns random access cycle time, 20 ns page mode (read only) cycle time Byte read/write control by UB/LB Wireless operating temperature range from -25 C to +85 C P-VFBGA-48 chip-scale package (8 x 6 ball grid)
Table 1
Product Selection
HYE18P16161AC
Min. Random Cycle time (tRC) Min. Page Read Cycle time (tPC) Operating current (Icc1) Stand-by current (Icc2) Ordering Info
-70
70ns 20ns 20mA 100uA
-85
85ns 25ns 17mA
L70
70ns 20ns 20mA 70uA
L85
85ns 25ns 17mA
(Contact Factory)
HYE
Extended Temp. part
18
P
1616
16M (x16 Org)
1
A
C
Chip Scale Package Design Revision number Device Type 1: Asynch/Page (48-ball)
VDD = 1.8 V typ.
PSRAM product
Data Sheet
8
V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Overview
1.2
General Description
The 16M Asynchronous/Page CellularRAM (CellularRAM) is is the competitive alternative to today's SRAM based solutions in wireless applications, such as cellular phones. With its high density 1T1C-cell concept and highly optimized low power design, the CellularRAM is the advanced economic solution for the growing memory demand in baseband IC designs. SRAM-pin compatibility, refresh-free operation and extreme low power design makes a drop-in replacement in legacy systems an easy procedure. Low power feature of Partial Array Self Refresh (PASR) allows the user to dynamically scale the active (=refreshed) memory to his needs and to adapt the refresh rate to the actual system environment. That is no power penalty is paid in case only portions of the total available memory capacity is used (e.g. 8Mb out of 16Mb). The CellularRAM is available in two package options, in the SRAM compatible FBGA 48-ball package and with an enhanced feature set in a FBGA 54-ball package. For the advanced 54-ball device please refer to the corresponding data sheet (HYE18P16160AC). The CelllularRAM can be powered from a single 1.8V power supply feeding the core and the output drivers. Feeding the I/Os with a separate voltage supply the CelllularRAM can be easily adapted to systems operating in an I/O voltage range from 1.8V to 3.0V. The chip is fabricated in Infineon Technologies advanced 0.14m low power process technology. The configuration of interfacing CellularRAM is illustrated in Figure 1. Data byte control (UB, LB) is featured in all modes and provides dedicated lower and upper byte access.
CS1 WE OE UB LB ZZ A20-A0
FBGA-48
DQ15-DQ0
CS1 WE OE UB LB ZZ A20-A0
FBGA-48
DQ15-DQ0
1.8V VDD 1.8V VDD & VDDQ 2.5V/ 3.0V VDDQ
(note) A20 is "don't care" in 16M CellularRAM
Figure 1
CellularRAM - Interface Configuration Options
The CellularRAM comes in a P-VFBGA-48 package.
Data Sheet
9
V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Overview
1.3
HYE18P16161AC(-/L)70/85 Ball Configuration
1 A B C D E F G H
LB DQ8 DQ9 VSSQ VDDQ DQ14 DQ15 A18
2
OE UB DQ10 DQ11 DQ12 DQ13 A19 A8
3
A0 A3 A5 A17 NC
(A21)
4
A1 A4 A6 A7 A16 A15 A13 A10
5
A2 CS1 DQ1 DQ3 DQ4 DQ5 WE A11
6
ZZ DQ0 DQ2 VDD VSS DQ6 DQ7 A20
A14 A12 A9
(note) A20 (ball "H6") is "don't care" in 16M CellularRAM
Figure 2
Standard Ballout - HYE18P16161AC(-/L)70/85
Note: Figure 2 shows top view
Data Sheet
10
V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Overview
1.4
Table 2 Ball CS1
HYE18P16161AC(-/L)70/85 Ball Definition and Description
Ball Description - HYE18P16161AC(-/L)70/85 Type Input Detailed Function Chip Select CS1 enables the command decoder when low and disables it when high. When the command decoder is disabled new commands are ignored, addresses are don't care and outputs are forced to high-Z. Internal operations, however, continue. For the details please refer to the command tables in Chapter 1.6. Output Enable OE controls DQ output driver. OE low drives DQ, OE high sets DQ to high-Z. Write Enable WE set to low while CS is low initiates a write command. Upper/Lower Byte Enable UB enables the upper byte DQ15-8 (resp. LB DQ7 ... 0) during read/write operations. UB (LB) deassertion prevents the upper (lower) byte from being driven during read or being written.
Deep Power Down Enable/ Set Control Register Strapping ZZ to low for more than 10s the device is put to deep power down mode. If a write access is initiated instantly (<500ns) after ZZ has been asserted to low access to the refresh configuration register is given. By applying the SET CONTROL REGISTER (SCR) command (see Table 3) the address bus is then loaded into the refresh control register.
OE WE UB, LB
Input Input Input
ZZ
Input
A <19:0> DQ <15:0> 1 x VDD 1 x VSS 1 x VDDQ 1 x VSSQ 2 x NC
Input I/O Power Supply Power Supply -
Address Inputs During a Control Register Set operation, the address inputs define the register settings. Data Input/Output The DQ signals 0 to 15 form the 16-bit data bus. Power Supply, Core Power and Ground for the internal logic. Power Supply, I/O Buffer Isolated Power and Ground for the output buffers to provide improved noise immunity. No Connect Please do not connect. Reserved for future use, i.e. H6: A20, E3: A21, see ballout in Figure 2 on Page 10.
Data Sheet
11
V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Overview
1.5
Functional Block Diagram
Address Decode
A19-A0
1T1C Cell Memory Array
1M x16
ZZ CS1 WE OE UB LB
Control Logic
Asynchronous SRAM I/F
DQ15-DQ8
DQ7-DQ0
Figure 3
Functional Block Diagram
Data Sheet
12
V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Overview
1.6
C
Commands
All commands are of asynchronous nature. The supported control signal combinations are listed in the table below. Table 3 Asynchronous Command Table Power Mode Active Active Active Standby~Active3) Standby Deep Power Down CS1 L L L L H H WE H L L H X X OE L X2) X
2)
Operation Mode READ WRITE SET CONTROL REGISTER NO OPERATION DESELECT DPD
UB/LB L
1)
ZZ H H L H X L
A19 V V L X X X
A18 - A0 ADR ADR RCR DIN X X X
DQ15:0 DOUT DIN X High-Z High-Z High-Z
L1) X X X X
H X X
1) Table 3 reflects the behaviour if UB and LB are asserted to low. If only either of the signals, UB or LB, is asserted to low only the corresponding data byte will be output or written (UB enables DQ15 - DQ8, LB enables DQ7 - DQ0). 2) During a write access invoked by WE set to low the OE signal is ignored. 3) Stand-by power mode applies only to the case when CS goes low from DESELECT while no address change occurs. Toggling address results in active power mode. Also, NO OPERATION from any active power mode by keeping CS low consumes the power higher than stand-by mode.
Note: `L' represents a low voltage level, `H' a high voltage level, `X' represents "Don't Care", `V' represents "Valid". Table 4 Mode READ Description of Commands Description The READ command is used to perform an asynchronous read cycle. The signals, UB and LB, define whether only the lower, the upper or the whole 16-bit word is output. The WRITE command is used to perform an asynchronous write cycle. The data is latched on the rising edge of either CS, WE, UB, LB, whichever comes first. The signals, UB and LB, define whether only the lower, the upper or the whole 16-bit word is latched into the CellularRAM. The control registers are loaded via the address inputs A15 - A0 performing an asynchronous write access. Please refer to the control register description for details. The SCR command can only be issued when the CellularRAM is in idle state. The NOP command is used to perform a no operation to the CellularRAM, which is selected (CS1 = 0). Operations already in progress are not affected. Power consumption of this command mode varies by address change and initiating condition. The DESELECT function prevents new commands from being executed by the CellularRAM. The CellularRAM is effectively deselected. I/O signals are put to high impedance state. DPD stops all refresh-related activities and entire on-chip circuit operation. Current consumption drops below 25 A. Wake-up from DPD also requires 150 s to get ready for normal operation.
WRITE
SET CONTROL REGISTER
NO OPERATION
DESELECT
DPD
Note: `L' represents a low voltage level, `H' a high voltage level, `X' represents "Don't Care", `V' represents "Valid".
Data Sheet
13
V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Functional Description
2
2.1
Functional Description
Power-Up and Initialization
The power-up and initialization sequence guarantees that the device is preconditioned to the user's specific needs. Like conventional DRAMs, the CellularRAM must be powered up and initialized in a predefined manner. VDD and VDDQ must be applied at the same time to the specified voltage while the input signals are held in "DESELECT" state (CS1 = High). After power on, an initial pause of 150 s is required prior to the control register access or normal operation. Failure to follow these steps may lead to unpredictable start-up modes.
VDD, VDDQ
VDD,VDDQ,min
t PU =150s
ready for normal operation
Figure 4
Power Up Sequence
Data Sheet
14
V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Functional Description
2.2
Access To The Control Register Map
[Disclaimer] A20 input shown in timing diagrams is not used in 16Mbit CellularRAM. Should be "don't care".
Write-only access to the refresh control register is enabled by applying the SCR command and asserting the ZZpin to low. Figure 5 shows the mapping of the address bus lines to the the refresh control register bits, whereas in Figure 6 the access timing is illustrated.
A19
A18
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
0
0
0
PM
TCSR
DPD
0
PASR
Control Register
Control Register Select A19 0 1 control reg RCR BCR
Page Mode Bit A7 0 1 page mode disabled (def.) enabled
Deep Power Down Mode A4 0 1 power down enabled disabled (def.)
Partial Array Self Refresh A2 0 0 0 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 refreshed memory area entire memory array (def.) (reserved) (reserved) lower 1/2 of memory array zero upper 1/2 of memory array (reserved) (reserved)
A18....A8, A3: reserved, must be set to '0'.
Temperature-Compensated Self-Refresh A6 1 0 0 1 A5 1 0 1 0 max. case temp. +85C (def.) +70C +45C +15C
0 1 1 1 1
Figure 5
Refresh Control Registers
A20-A0
RCR OPCODE
Close Latch CS1 Open Latch
UB, LB
WE Initiate Control Register Access
ZZ
DQ15-DQ0
Don't Care
(note) A20 is "don't care" in 16M CellularRAM
Figure 6
Control Register Write Access Protocol
Data Sheet
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V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Functional Description
2.3
Refresh Control Register
The Refresh Control Register (RCR) allows to save stand-by power additionally by making use of the Temperature-Compensated Self Refresh (TCSR), Partial-Array Self Refresh (PASR) and Deep Power Down (DPD) features. The Refresh Control Register is programmed via the Control Register Set command and retains the stored information until it is reprogrammed or the device loses power. Please note that the RCR contents can only be set or changed when the CellularRAM is in idle state. RCR Refresh Control Register
A19 RS A18 A17 A16 A15
(ZZ, A19 = 00B)
A14 A13 A12 A11 A10 0 A9 A8 A7 PM A6 A5 A4 DPD A3 0 A2 A1 PASR A0
TCSR
Field RS PM
Bits 19 7
Type1) Description w w Register Select 0 set to 0 to select this RCR. Page Mode Enable/Disable In asynchronous operation mode the user has the option to toggle A0 - A3 in a random way at higher rate (20 ns vs. 70 ns) to lower access times of subsequent reads with 16-word boundary. In synchronous mode this option has no effect. The max. page length is 16 words. Please note that as soon as page mode is enabled the CS1 low time restriction applies. This means that the CS1 signal must not be kept low longer than tCSL = 10 s. Please refer to Figure 11. 0 page mode disabled (default) 1 page mode enabled Temperature Compensated Self Refresh The 2-bit wide TCSR field features four different temperature ranges to adjust the refresh period to the actual case temperature. Since DRAM technology requires higher refresh rates at higher temperature this is a second method to lower power consumption in case of low or medium temperatures. 11 +85 C (default) 00 +70 C 01 +45 C 10 +15 C Deep Power Down Enable/Disable The DPD control bit puts the CellularRAM device in an extreme low power mode cutting current consumption to less than 25 A. Stored memory data is not retained in this mode, while the settings of control register, RCR is stored during DPD. 0 DPD enabled 1 DPD disabled (default)
TCSR
[6:5]
w
DPD
4
w
Data Sheet
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HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Functional Description Type1) Description w Partial Array Self Refresh The 3-bit PASR field is used to specify the active memory array. The active memory array will be kept periodically refreshed whereas the disabled parts will be excluded from refresh and previously stored data will get lost. The normal operation still can be executed in disabled array, but stored data is not guaranteed. This way the customer can dynamically adapt the memory capacity in steps of 8 Mbit to one's need without paying a power penalty. Please refer to Figure 7. 000 entire memory array (default) 011 lower 1/2 of the memory array (8 Mb) 100 zero 101 upper 1/2 of the memory array (8 Mb) All others; reserved (16Mb) Reserved must be set to `0'
Field PASR
Bits [2:0]
Res
[18:8], 3
w
1) w: write-only access
2.3.1
Partial Array Self Refresh (PASR)
By applying PASR the user can dynamically customize the memory capacity to one's actual needs in normal operation mode and standby mode. With the activation of PASR there is no longer a power penalty paid for the larger CellularRAM memory capacity in case only e.g. 8 Mbits are used by the host system. Bit2 down to bit0 specify the active memory array and its location (starting from bottom or top). The memory parts not used are powered down immediately after the mode register has been programmed. Advice for the proper register setting including the address ranges is given in Figure 7.
PASR.Bit2,1,0
8M 0M
FFFFFh FFFFFh
101
100
8M
80000h
7FFFFh 00000h
8M
00000h
011
8M
000
16M
PASR.Bit2,1,0
Figure 7
PASR Programming Scheme
PASR is activated, i.e. the memory parts not used are powered down, after ZZ has been held low for more than 10s. In PASR state no READ or WRITE commands are recognized. To resume WRITE or READ operations, the device must exit PASR by taking ZZ to high level voltage again. Pre-condition to enter PASR on ZZ low is that the Deep Power Down mode has been disabled before via RCR.Bit4= 1. Figure 8 shows an exemplary PASR configuration where it is assumed that the application uses max. 8 Mbit out of 16 Mbit.
Data Sheet
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V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Functional Description
16Mb CellularRAM 8Mb Deactivated
07FFFFh 000000h
Active Memory Array defined by PASR to 8Mb RCR.Bit 2,1,0= 011
8M Activated
Figure 8
PASR Configuration Example
2.3.2
Deep Power Down Mode
To put the device in deep power down mode, it is required to comply with 2-steps. At first, the DPD mode bit must be set to be enabled in the Refresh Configuration Register. When DPD entry is really required, ZZ pin must be asserted to low for longer than 10s. Between these 2 steps, any normal operations are permitted. Once the device enters into this extreme low power mode, current consumption is cut down to less than 25A. All internal voltage generators inside the CelllularRAM are switched off and the internal self-refresh is stopped. This means that all stored information will be lost in any time. The device will remain in DPD mode as long as ZZ is held low.To exit the Deep Power Down mode, it is needed to simply bring ZZ to high voltage level. A guard time of at least 150s has to be met where no commands beside DESELECT must be applied to re-enter standby or idle mode. (see Figure 16).
2.3.3
Temperature Compensated Self Refresh (TCSR)
The 2-bit wide TCSR field features four different temperature ranges to adjust the refresh period to the actual case temperature. DRAM technology requires higher refresh rates at higher temperature. At low temperature the refresh rate can be reduced, which reduces as well the standby current of the chip. This feature can be used in addition to PAR to lower power consumption in case of low or medium temperatures. Please refer to Table 5.
2.3.4
Power Saving Potential in Standby When Applying PASR, TCSR or DPD
Table 5 demonstrates the currents in standby mode when PASR, TCSR or DPD is applied. Table 5 Operation Mode NO OPERATION/ DESELECT DPD Standby Currents When Applying PASR, TCSR or DPD Power Mode STANDBY PASR TCSR PASR Bit Controlled RCR.Bit6-5 RCR.Bit2-0 Wake-Up Phase - - Active Array - Full 1/2 0 0 85 Standby [A] 70 45
55(70) 53(65) 50(60)
15
50(60) 50(60) 50(60)
70(100) 65(90) 60(80) 60(75) 50(60) 50(60)
DEEP POWER DPD DOWN
RCR.Bit4
~150 s
25.0
Data Sheet
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V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Functional Description
2.3.5
Page Mode Enable/Disable
In asynchronous operation mode, the user has the option to enable page mode to toggle A0 - A3 in random way at higher cycle rate (20 ns vs. 70 ns) to lower access times of subsequent reads within 16-word boundary. Write operation is not supported in the manner of page mode access. In synchronous mode, this option has no effect. The max. page length is 16 words, so which A0 - A3 is regarded as page-mode address. If the access needs to cross the boundary of 16-word (any difference in A18 - A4), then it should start over new random access cycle, which is the same as asynchronous read operation. Please note that as soon as page mode is enabled the CS1 low time restriction applies. This means that the CS1 signal must not kept low longer than tCSL = 10 s. Please refer to Figure 11.
Data Sheet
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V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Functional Description
2.4
Asynchronous Read
[Disclaimer] A20 input shown in timing diagrams is not used in 16Mbit CellularRAM. Should be "don't care".
The CellularRAM applies the standard asynchronous SRAM protocol to perform read and write accesses. Reading from the device in asynchronous mode is accomplished by asserting the Chip Select (CS1) and Output Enable (OE) signals to low while forcing Write Enable (WE) to high. If the Upper Byte (UB) control line is set active low then the upper word of the addressed data is driven on the output lines, DQ15 to DQ8. If the Lower Byte (LB) control line is set active low then the lower word of the addressed data is driven on the output lines, DQ7 to DQ0.
tRC
A20-A0
tOH tAA
ADDRESS
DQ15-DQ0
Previous Data
Data Valid
Not Valid
(note) A20 is "don't care" in 16M CellularRAM
Figure 9
Asynchronous Read - Address Controlled (CS1 = OE = VIL, WE = VIH, UB and/or LB = VIL, ZZ = VIH)
tRC
A20-A0
tAA
ADDRESS tOH tCO tCPH
CS1
UB, LB
tBA tBPH
WE
tHZ tBHZ tOE tOLZ tBLZ tOHZ Data Valid
OE
DQ15-DQ0
Don't Care
tLZ
(note) A20 is "don't care" in 16M CellularRAM
Figure 10
Asynchronous Read (WE = VIH, ZZ = VIH)
Data Sheet
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V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Functional Description
2.4.1
Page Read Mode
If activated by RCR.Bit7 page mode allows to toggle the four lower address bits (A3 to A0) to perform subsequent random read accesses (max. 16-words by A3 - A0) at much faster speed than 1st read access. Page mode operation supports only read access in CellularRAM. As soon as page mode is activated, CS1 low time restriction (tCSL ) applies. In case of CS1 staying low longer than tCSL limit, then it is alternative way to toggle non-page address (A18 - A4) no later than tCSL,max. Therefore the usage of page mode is only recommended in systems which can respect this limitation. Please see also application note on Page 30.
tRC
A20-A4
ADDRESS tPC
A3-A0
ADDRESS tAA
ADR
ADR
ADR
ADR
CS1
tCO tCSL tHZ
UB, LB
tBHZ
WE
tBLZ
OE
tOLZ tOH Data Data tPAA Data Data Data tOHZ tLZ
DQ15-DQ0
Don't Care
(note) A20 is "don't care" in 16M CellularRAM
Figure 11
Asynchronous Page Read Mode (ZZ = VIH)
Data Sheet
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V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Functional Description Table 6 Parameter Read cycle time Address access time Page address cycle time Page address access time Output hold from address change Chip select access time UB, LB access time OE to valid output data Chip select pulse width low time Chip select to output active Chip select disable to high-Z output UB, LB enable to output active UB, LB disable to high-Z output Output enable to output active Output disable to high-Z output CS1 high time when toggling UB, LB high time when toggling Timing Parameters - Asynchronous Read Symbol Min. 70 Max. - 70 - 20 - 70 70 20 10 - 8 - 8 - 6 - - Min. 85 - 25 - 6 - - - - 6 - 6 - 3 - 15 15 70 - 20 - 5 - - - - 6 - 6 - 3 - 10 10 85 Max. - 85 - 25 - 85 85 25 10 - 8 - 8 - 8 - - ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns - - - - - - - - - - - - - - - - - Unit Notes
tRC tAA tPC tPAA tOH tCO tBA tOE tCSL tLZ tHZ tBLZ tBHZ tOLZ tOHZ tCPH tBPH
Data Sheet
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V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Functional Description
2.5
Asynchronous Write
Writing to the device in asynchronous mode is accomplished by asserting the Chip Select (CS1) and Write Enable (WE) signals to low. If the Upper Byte (UB) control line is set active low then the upper word (DQ15 to DQ8) of the data bus is written to the specified memory location. If the Lower Byte (LB) control line is set active low then the lower word (DQ7 to DQ0) of the data bus is written to the specified memory location. Write operation takes place when either one or both UB and LB is asserted low. The data is latched by the rising edge of either CS1, WE, or UB/LB whichever signal comes first.
tWC
A20-A0
ADDRESS tAW tWR tCW
CS1
UB, LB
tBW tWPH
WE
tAS
tWP tDW tDH Data Valid tWHZ tOW
DQx IN
DQx OUT
Don't Care
(note) A20 is "don't care" in 16M CellularRAM
Figure 12
Asynchronous Write - WE Controlled (OE = VIH or VIL, ZZ = VIH)
tWC
A20-A0
ADDRESS tAW tWR tCW tCPH tBW
CS1
tAS
UB, LB
WE
tWP tDW tDH Data Valid tWHZ
DQx IN
DQx OUT
Don't Care
(note) A20 is "don't care" in 16M CellularRAM
Figure 13
Asynchronous Write - CS1 Controlled (OE = VIH or VIL, ZZ = VIH)
Data Sheet
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V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Functional Description
tWC
A20-A0
ADDRESS tAW tWR tCW tAS tBPH tBW
CS1
UB, LB
WE
tWP tDW tDH
DQx IN
tWHZ tBLZ, tLZ
Data In Valid
DQx OUT
Don't Care
High-Z
(note) A20 is "don't care" in 16M CellularRAM
Figure 14
Asynchronous Write - UB, LB Controlled (OE = VIH or VIL, ZZ = VIH)
The programming of control register in asynchronous mode is performed in the similar manner as asynchronous write except ZZ being held low during the operation. Note that ZZ has to meet set-up time (tZZWE) and hold time (tWEZZ)of valid state (= Low) in reference to WE falling and rising edge, respectively. CS1 should toggle at the end of the operation to get ready for following access.
t WC
A20-A0
RCR OPCODE t AW tWR tCW
CS1
UB, LB
WE
t CDZZ
tAS tZZWE
tWP
tWPH
ZZ
tWEZZ
DQx IN
High-Z
DQx OUT
Don't Care
High-Z
(note) A20 is "don't care" in 16M CellularRAM
Figure 15 Data Sheet
Asynchronous Write to Control Register (OE = VIH or VIL) 24 V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Functional Description Table 7 Parameter Write cycle time Address set-up time to start of write Address valid to end of write Write recovery time Chip select pulse width low time Chip select to end of write Byte control valid to end of write Write pulse width Write pulse pause CS high time when toggling UB, LB high time when toggling Write to output disable End of write to output enable Write data setup time Write data hold time CS1 high setup time to ZZ low ZZ active setup time to start of write ZZ active hold time from end of write Timing Parameters - Asynchronous Write Symbol Min. 70 Max. - - - - 10 - - - - - - 8 - - - - 500 - Min. 85 0 85 0 - 85 85 45 15 15 15 - 3 20 0 5 10 0 70 0 70 0 - 70 70 40 10 10 10 - 3 20 0 5 10 0 85 Max. - - - - 10 - - - - - - 10 - - - - 500 - ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns - - - - - - - - - - - - - - - - - - Unit Notes
tWC tAS tAW tWR tCSL tCW tBW tWP tWPH tCPH tBPH tWHZ tOW tDW tDH tCDZZ tZZWE tWEZZ
Data Sheet
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V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Functional Description
2.6
Deep Power Down Mode Entry/ Exit
To put the device in deep power down mode, it is required to comply with 2-step operation. At first, the DPD mode bit (RCR.bit4) has be programmed to be enabled in the Refresh Configuration Register through SCR command. When DPD entry is really required, ZZ pin must be asserted to low for longer than 10s while CS1 sets to high as shown in Figure 15. Between these 2 steps, any normal operations are permitted. Once the device enters into this extreme low power mode, current consumption is cut down to less than 25A. Please note that 2 step operation for DPD entry is not designed to take place at a time when ZZ is held low. In case of back-to-back operation to perform 2 steps, it is required to meet ZZ precharge time (tZPH). All internal voltage generators inside the CelllularRAM are switched off and the internal self-refresh is stopped. This means that all stored information will be lost in any time. The device will remain in DPD mode as long as ZZ is held low. To exit the Deep Power Down mode, it is needed to simply bring ZZ to high voltage level. A guard time of at least 150s (tR) has to be met where no commands beside DESELECT must be applied to re-enter standby or idle mode. Figure 16 Deep Power Down Entry/ Exit
(/ZZ high time is required between step 1 and 2) (any normal operation is allowed in between)
CS1
tCDZZ tR
ZZ
tZPH
tZZMIN
Entering DPD Step 1 (SCR) RCR.bit4 should be programmed to enable DPD Step 2 /ZZ low for longer than tZZmin
Device in DPD (maintaining)
Exiting DPD
Don't Care
Table 8 Parameter
DPD/ ZZ Timing Table Symbol Min. 70 & 85 Max. - - - - ns ns s s - - - - 5 5 10 150 Unit Notes
CS1 high setup time to ZZ low ZZ precharge time ZZ active for DPD entry Recovery time from DPD exit
tCDZZ tZPH tZZMIN tR
2.7
General AC Input/Output Reference Waveform
The input timings refer to a midlevel of VDDQ/2 while as output timings refer to midlevel VDDQ/2. The rising and falling edges are 10 - 90% and < 2 ns.
Data Sheet
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V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Electrical Characteristics
3
3.1
Table 9 Parameter
Electrical Characteristics
Absolute Maximum Ratings
Absolute Maximum Ratings Symbol Limit Values Min. Max. +85 +150 260 +2.45 +3.6 +3.6 180 +50 C C C V V V mW mA - - - - - - - - -25 -55 - -0.3 -0.3 -0.3 - -50 Unit Notes
Operating temperature range Storage temperature range Soldering peak temperature (10 s) Voltage of VDD supply relative to VSS Voltage of VDDQ supply relative to VSS Voltage of any input relative to VSS Power dissipation Short circuit output current
TC TSTG TSold VDD VDDQ VIN PD IOUT
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
3.2
Recommended Power & DC Operation Ratings
All values are recommended operating conditions unless otherwise noted. Table 10 Parameter Power supply voltage, core Power supply voltage, 1.8 V I/Os Power supply voltage, 2.5 V I/Os Power supply voltage, 3.0 V I/Os Input high voltage Input low voltage Table 11 Parameter Output high voltage (IOH = -0.2 mA) Output low voltage (IOL = 0.2 mA) Input leakage current Output leakage current DC Characteristics Symbol Min. Limit Values Typ. - - - - Max. - V V A A - - - - Unit Notes Recommended DC Operating Conditions Symbol Min. Limit Values Typ. 1.8 1.8 2.5 3.0 - - Max. 1.95 2.25 2.7 3.3 V V V V V V - - - - - - 1.7 1.7 2.3 2.7 Unit Notes
VDD VDDQ VDDQ VDDQ VIH VIL
VDDQ - 0.4
-0.2
VDDQ + 0.2
0.4
VOH VOL ILI ILO
VDDQ x 0.8
- - -
VDDQ x 0.2
1 1
Data Sheet
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V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Electrical Characteristics Table 12 Parameter Operating Characteristics Symbol Min. Operating Current IDD1 * Async read/write random @tRCmin * Async read/write random @tRC = 1 s IDD1L * Async Page read IDD1P Stand-By Current : L-part (16M) Stand-By Current : Std. part (16M) - - - - - 70 Max. 20 5 15 70 100 Min. - - - - - 85 Max. mA 17 5 12 70 100 A A A Unit Test Condition Notes
1)
Vin = VDD or VSS, Chip
enabled, Iout = 0
IDD2
Vin = VDD or VSS, Chip
deselected, (Full array)
-
Deep Power Down Current (16M)
IDD3
-
25
-
25
Vin = VDD or VSS
-
1) The specification assumes the output disabled.
3.3
Output Test Conditions
VDDQ
5.4kOhm
DUT
5.4kOhm 30pF
Test point
VSSQ
VSSQ
Figure 17
Output Test Circuit
Please refer to section Section 2.7.
3.4
Table 13 Pin
Pin Capacitances
Pin Capacitances Limit Values Min. Max. 5.0 6.0 pF pF - - Unit Condition
A19 - A0, CS1, OE, WE, UB, LB, ZZ DQ15 - DQ0
TA = +25 C freq. = 1 MHz Vpin = 0 V (sampled, not 100% tested)
Data Sheet
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V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Package Outlines
4
Package Outlines
Figure 18
P-VFBGA-48 (Plastic Very Thin Fine Pitch Ball Grid Array Package)
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 29 Dimensions in mm V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Appendix A: Low-Frequency Mode
5
5.1
Appendix A: Low-Frequency Mode
Asynchronous Access
Depending on the random access frequency two cases are distinguished: High Frequency Mode ( 100 kHz): There are no tRC max. time nor CS1/OE max. low time restrictions during subsequent random read or write accesses. Low Frequency Mode (< 100 kHz): There are no tRC max. time nor CS1/OE max. low time restrictions if all control signals (CS1, OE, WE, UB/LB) follow the modified timing as shown below, see attached timing diagram and timing table. There is no extra mode register setting necessary.
tARV
tAWV ADDRESS
A20-A0
CS1
tAA
WE
tWPV tDWV Data Valid
DQ<15:0>
Data Valid
(note) A20 is "don't care" in 16M CellularRAM
Figure 19 Parameter
Low Frequency Mode Symbol Min. 70 Max. - - - - Min. 85 85 85 85 70 70 70 70 85 Max. - - - - ns ns ns ns - - - - Unit Notes
Address stable time for read access Address stable overlap with write pulse Write pulse width Data to write time overlap
tARV tAWV tWPV tDWV
Data Sheet
30
V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Appendix B: S/W Register Entry Mode ("4-cycle method")
6
Appendix B: S/W Register Entry Mode ("4-cycle method")
Other than ZZ-controlled SCR operation, CellularRAM supports software (S/W) method as an alternative to access the control registers. Since S/W register entry mode consists of 4 consecutive access cycles to top memory location (all addresses are "1"), it is often referred as "4-cycle method". 4-cycles starts from 2 back-to-back read cycles (initializing command identification) followed by one write cycle (command identification completed and refresh control register is accessed), then final write cycle for configuring the RCR by the given input or read cycle to check the content of the register through DQ pins. It does function the configuration of control register bits like the way with dedicated pin, ZZ method, but there are a few differences from ZZ-controlled method as follow; * * Register read mode (checking content) is supported with S/W register entry as well as register write (program). The mode bits for control register are supplied through DQ <15:0> instead of address pins in ZZ-controlled. Though each register has 20-bits (A<19:0>) for 16M CellularRAM, only low 16-bit registers becomes valid during S/W method. The valid selection of refresh control register, RCR, is done with the state of DQ<15:0> given at 3rd cycle. ("00h") Since S/W register entry asks for 4 complete access cycles in a row and the device is designed operating with internally regulated supply which is going to be discharged in deep power-down (DPD) mode, DPD function is not supported with this programming method. The method is realized by the device exactly when 2 consecutive read cycles to top memory location is followed by write cycle to the same location, so that any exceptional cycle combination - not only access mode, but also the number of cycles - will fail in invoking the register entry mode properly.
* *
*
tRC Amax-A0
tWC
All "1"s
All "1"s
All "1"s
All "1"s
ADV# CS
UB, LB
WE OE
DQ15-DQ0 (Cycle Type) (Function) Read to top memory location (1st) Read to top memory location (2nd) Wait for next write to confirm S/W register entry
0000h(RCR)
Register bits
Write to top memory location Select RCR
Write or Read to top memory location (Write) Configure RCR by DQ inputs (Read) Output RCR contents through DQ
Don't Care
Figure 20
S/W Register Entry timing (Address input = FFFFFh)
Data Sheet
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V2.0, 2003-12-16
HYE18P16161AC(-/L)70/85 16M Asynch/Page CellularRAM
Appendix B: S/W Register Entry Mode ("4-cycle method")
D15
D8
D7
D6
D5
D4
D3
D2
D1
D0
DQ<15:0>
0
0
PM
TCSR
DPD*
0
PASR
Control Register
Page Mode Bit D7 0 1 page mode disabled (def.) enabled
Deep Power Down Mode D4 X power down disabled (def.)
Partial Array Self Refresh D2 0 0 0 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 refreshed memory area entire memory array (def.) (reserved) (reserved) lower 1/2 of memory array zero upper 1/2 of memory array (reserved) (reserved)
D15....D8, D3: reserved, must be set to '0'.
Temperature-Compensated Self-Refresh D6 1 0 0 1 D5 1 0 1 0 max. case temp. +85C (def.) +70C +45C +15C
0 1 1 1 1
Figure 21
RCR Mapping in S/W Register Entry
Data Sheet
32
V2.0, 2003-12-16
www.infineon.com
Published by Infineon Technologies AG

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